2017 Call for Papers (download)

The IEEE SOI-3D-Subthreshold Microelectronics Technology
Unified Conference (IEEE S3S)

2017 IEEE S3S Call for Papers

New Deadline: June 12, 2017, 11:59pm PST

Papers in the following areas are requested:
Silicon on Insulator (SOI)
Low-Voltage Microelectronics
3D Integration

Silicon-on-Insulator (SOI)

For over 35 years our conference has been the premier meeting of engineers and scientists dedicated to current trends in Silicon-On-Insulators technology. Papers are solicited in all areas of SOI technology and related devices, circuits and applications, including:
• Device Physics and Modeling
• High-Voltage Devices
• Advanced Materials, Substrates & Process Integration
• Photonics
• New SOI Structures, Circuits and Applications
• Asynchronous Circuits
• Sensors, NEMS, MEMS
• SOI and FDSOI Manufacturability and Process Integration
• Substrate Engineering
• Fully-Depleted / Thin-Body Devices
• Analog and RF Technologies
• SOI Circuit Applications
• Device Reliability and Characterization
• RFID Technology and Applications
• SOI-specific Design

Low-Voltage Microelectronics

Ultra-low-power/Ultra-low-voltage microelectronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. Papers are solicited in the following technical focus areas, but research or concepts in any area of low-voltage microelectronics will be considered:
• Unattended Remote Sensors
• Space-Based Sensors
• Biomedical Devices
• Low-Voltage Handheld/wireless systems
• Ultra-Low-Power Digital Computation
• Analog and RF Technologies
• Energy Management Circuits
• Low Voltage Memory Technologies
• Radiation Effects
• Transistor Variability and Mitigation
• Energy Harvesting Techniques
• Asynchronous Circuits
• Novel Device and Fabrication Technology
• Robust Circuit Design

3D Integration

3D Integration, including monolithic 3D IC or sequential 3D IC, allows us to scale integrated circuits “orthogonally” in addition to classical 2D device and interconnect scaling. We will cover fabrication techniques, bonding methods as well as design and test methodologies. Novel inter-strata interconnect schemes will also be discussed. Previously unpublished papers are solicited in all of the above areas related to 3D implementation including:
• Low Thermal Budget Processing
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technology
• Heterogeneous substrates, devices and architectures
• 3D manufacturing and Logistics
• Reliability of 3D Circuits
• Cost Analysis of 3D Architectures
• Fault Tolerant 3D Designs

Download the 2017 Call for Papers Deadline Extended to June 12, 2017
Preparation of Abstracts
How to submit your abstract 

(c) Copyright 2015 Joyce Lloyd, IMF