The IEEE SOI-3D-Subthreshold Microelectronics Technology
Unified Conference (IEEE S3S)
Paper Submission Closed on 18 May, 2015
Late News Papers Deadline Extended to 11:59 pm PST, 31 August, 2015
Now in its 3rd year as a combined event, the 2015 IEEE S3S Conference will take place in Sonoma Valley, CA, just north of San Francisco. This industry-wide event will gather together widely known experts, contributed papers and invited talks on 3 main topics: SOI technology, subthreshold architectures with associated designs and 3D integration. Combining those three topics enables us to provide extensive and high quality technical content, and makes the conference the perfect venue to present and learn about the most up to date trends in CMOS and post-CMOS Scaling and the low-power SOC eco-system.
The IEEE S3S organizers are pleased to welcome you to this exciting event, which allows attendees to access essentially three conferences with one registration fee.
This year our conference will host parallel tracks for SOI Technology and Subthreshold Microelectronics, complemented by two short courses and two fundamentals classes. In addition, we will feature 3D Integration by having a joint technical session exclusively dedicated to this topic as well as a short course detailing the basics and latest trends in this exciting field.
The usual Hot Topics, Rump and Poster sessions will of course be part of the program, as well as the social events tailored to give much appreciated networking and discussions opportunities. While extended content is made available, we will continue to be the world’s premier conference to present and discuss state of the art SOI technical papers.