This tutorial is included with your conference registration. You can also access it by registering for the Tuesday Only membership. Please visit our Registration Page for additional information.

Introduction
Chair: Maud Vinet, CEA-Leti

An alternative or complementary approach to conventional scaling of planar integration for future nodes is the
3D integration. There are several approaches for 3D scaling and our short course will focus on the high density
ones. The short course will review the technological achievments, opportunities and challenges for high density
3D integrations. It will present design tools and methodology developed to evaluate the gain of 3D integration;
Finally thoughts on yield and cost assessment for these high density 3D integrations will be shared.

Technological approaches to 3D CMOS integration
Zvi Or-Bach, MonolithIC 3D

The challenge for Monolithic 3D IC is how to provide high quality transistor on top of prefabricated structure
without impairing by the high temperature process steps which are usually associated with the formation of
high quality transistor.
1. Forming the silicon layer: Recrystallization, layer transfer
2. Forming transistors: Split hot/cold, shield the underlying structure,
3. Transfer yet align: Smart process, precise bonder, smart alignment
4. Non CMOS transistors: CNT, mechanical.

3D co-integration opportunities for high mobility materials
Lukas Czornomaz, IBM

Pure geometrical scaling does not anymore bring the expected power/performance benefits. In the past decade,
the industry has gradually moved to innovation-driven scaling bringing to the market chips based on
strained silicon, silicon-on-insulator, high-k/metal gate technology and tri-gate devices. This trend will continue
by the move to 3D integration and high-mobility channel materials such as SiGe and III-V compound semiconductors
that will need to be co-integrated on the same platform. We will review the material integration
strategies, as well as device and circuit integration challenges, showing that 3D integration is not only an opportunity
for further density scaling, but it also offers unique advantages for solving the integration of high
mobility materials.

Monolithic 3D design methodology
Olivier Billoint, CEA-Leti

Based on our exploration of 3D sequential digital design opportunities, an overview of CoolcubeTM design
methodologies will be presented. Starting from a RTL netlist, we will detail the different process flavors with
associated constraints on standard cells and SRAM memories for SoC implementation. Both transistor-level
and gate-level 3D physical implementation techniques will be covered with an emphasis on flow complexity
and tool availability.

Design and CAD Methodologies to Tackle FEOL/BEOL Degradation in Monolithic 3D ICs
Sung-Kyu Lim, Georgia Tech

Yield and cost aspects of CoolCube(TM) integration
Daniel Gitlin, Independant Consultant

Based on the well known Bose-Einstein yield model, a cost model for monolithic 3D-ICs will be presented. The
model takes into account increased process complexity and associated yield impact as well as area reduction.
As 3D-IC manufacturing architecture and technology details are narrowed and partitioning schemes as well
design methodologies are chosen, the model parameters can be adjusted accordingly and the trade offs studied.
Numerous examples are discussed to illustrate the model usage. This model enables more accurate cost
modeling and therefore PPC (Power, Performance and Cost) understanding and the range of applicability for
monolithic 3D-IC technology. The model shows that depending on the die area and partitioning scheme, the
cost benefits can be 50% or higher.

3D scaling opportunities and challenges from a design and technology point of view
Praveen Raghavan, IMEC

3D scaling brings forward various aspects of challenges for design and technology. It is important that we
perform the co-optimization of both the 3D technology along with the design. This talk will talk about the
performance-power-cost challenges of doing monolithic 3d and under which conditions monolithic 3D would
be superior. Both the process challenges as well as the design challenges would be discussed to illustrate the
advantages and disadvantages of monolithic 3D compared to 2D scaling.

This tutorial is included with your conference registration. You can also access it by registering for the Tuesday Only membership. Please visit our Registration Page for additional information.

FD-SOI technology for IoT SoCs: interfacing sensors and connecting to the world
Chairs: Carlos Mazure, SOITEC and Giorgio Cesana, STMicroelectronics

Advanced CMOS technologies are the key enablers of Internet of Things applications, allowing the integration of heterogeneous functions on complex system-on-chip. IoT is not exactly a new set of applications: it is the capability of connecting simple devices to allow extending their features capitalizing on the data collected and transmitted. To offer such extended features, “objects” must be connected to a network infrastructure from where they can take additional information to accomplish a specific task, and cloud compute on the data generated.

From the “object” point of view, we need to put together three functions: the capability of collecting data from the environment, elaborate on it, and communicating between objects and/or the cloud, all those operations having to be performed with the highest possible energy efficiency.

The unique requirements of IoT nodes (low cost, low power/energy, small form factor, co-integration of complex functions, RF connectivity, local data processing for simplification…) require the ability to co-integrate energy efficient low voltage digital performances with excellent RF capabilities and analog interfaces to sensors.

FD-SOI technology is showing promising features: while literature has focused in the past on the digital features and the energy efficiency of this technology, it is of paramount importance the ability of interfacing with sensors as well as wirelessly transmitting data. The scope of this short course is to introduce the audience to the technology features and design examples for AMS/RF applications.

The short course articulates as following:

An introduction on IoT applications requirements, architectures
Vidyasager Ganesan, Invecas

An overview on the FD-SOI technology and its intrinsic features
Ali Khakifirooz, Intel

A deep dive on AMS and RF technology capabilities and circuit examples: from simple analog/RF/mmW design examples to full RF-AMS-digital SoC integration
Andreia Cathelin, STMicroelectronics

A deep dive on AMS and RF design flows to tackle design challenges
Helen Beckrich Ros, STMicroelectronics

An overview on application examples
Vidyasagar Ganesan, Invecas

A round table to sum up the afternoon and draw some joint conclusions and take-away