Executive Director, SOI Industry Consortium
Jon Cheek is currently Senior Director at NXP Semiconductor in the Process Technology Department. He started his career at Advance Micro Devices doing high performance transistor development. After 11 years at AMD, he moved to Freescale Semiconductor where he led the development of both high performance PD-SOI CMOS and embedded non-volatile memory technologies. Starting in 2015, with Freescale becoming NXP, he now leads the SPICE model development group.
Beginning in 2019, Jon joined the SOI Industry Consortium as Co-Executive Director. He actively works with member companies to promote, educate, and connect the users of SOI technology across the industry.
CTO and Vice President, Worldwide Client Solutions, GLOBALFOUNDRIES
Subramani is currently the CTO and Vice President of World-Wide Client Solutions responsible for enabling differentiated solutions and providing technical support for World-wide Clients. As the Primary technical interface, his Global team is chartered with ensuring GLOBALFOUNDRIES’ Clients can Innovate and Differentiate to full technology entitlement to lead in their respective Markets.
Subramani joined GLOBALFOUNDRIES in 2009 as the Vice President of Design Solutions. Most recently, he was the Vice President of CMOS Platforms BU responsible for business results across Advanced technology nodes at Fab1 (Germany) in support of world-wide customers and company’s financial objective. Prior to that, he was the Vice President of Global Design Solutions responsible for world-wide design engineering, semiconductor design eco-system development and design-technology co-optimization. His team enabled IP, EDA and SoC solutions in support of “first time right” technology qualification and customer SoC differentiation. His team was also responsible for determining technology feasibility, competitiveness and manufacturability of technology platform through design-technology Interactions with customers, technology R&D and design eco-system. As the Head of Advanced Technology Architecture, in the Office of the CTO, Subramani was responsible for defining competitive 22FDSOI, 14nm, 10nm and 7nm technology platforms.
Subramani started his VLSI design engineering career at Texas Instruments and prior to joining GLOBALFOUNDRIES, he was the Senior Director of design and technology platform at TSMC. Subramani has over 28 years semiconductor industry experience and has been granted 45 U.S. patents. He holds a Master’s degree in electrical engineering from Indian Institute of Technology (IIT, Delhi) and a certificate in executive management from AeA/Stanford University
PDF Fellow at PDF Solutions
Tomasz Brozek is a Technical Fellow and Senior Director at PDF Solutions, Santa Clara, California, where he is responsible for advanced silicon technology characterization, diagnostic methods development, and early yield ramp of integrated circuits. Since joining the company in 2000, he led multiple projects covering Logic, Memory (DRAM, Flash, 3D NAND, Emerging Memories), and Image Sensor.
He holds an MS EE and a Ph.D in physics. His doctorate research at the Institute of Semiconductor Physics in Kiev, Ukraine focused on radiation effects and degradation in microelectronic MOS systems. Previously he taught and conducted research at Warsaw University of Technology, Poland and the University of California, Los Angeles, USA, and worked at Motorola R&D organizations in Texas and Arizona, USA.
Dr. Brozek published more than 70 papers and conference presentations, and holds several patents. He has served on numerous Committees of IEEE Conferences, among them Plasma Process –Induced Damage, International Reliability Physics Symposium, and Electron Device Technology and Manufacturing.
Fellow at STMicroelectronics
Andreia Cathelin is Technology R&D Fellow with STMIcrolectronics in Crolles, France. She started electrical engineering studies at the Polytechnic Institute of Bucarest, Romania and graduated with MS from the Institut Supérieur d’Electronique du Nord (ISEN), Lille, France in 1994. In 1998 and 2013 respectively, she received PhD and “habilitation à diriger des recherches” (French highest academic degree) from the Université de Lille 1, France.
Since 1998, she has been with ST, where her focus areas are in the design of RF/mmW/THz and ultra-low-power circuits and systems. She is the key design scientist in the promotion of all advanced CMOS technologies developed in the company and has an active participation in the frame of the SOI Consortium, an industrial group federating SOI technologies ecosystem.
Andreia has had numerous responsibilities inside the IEEE community since more than 10 years. At ISSCC, she has been the RF sub-committee chair from 2012 to 2015, and since 2016 is the Forums Chair and member of the Executive Committee. She is member of ESSCIRC TPC since 2005. Since September 2013, Andreia is on the Steering Committee of ESSCIRCESSDERC conferences, where she has been the Chair from 2015 to September 2017. She has served different positions on the Technical Program Committees of VLSI Symposium on Circuits from 2010 till 2016.
Andreia has authored or co-authored 130+ technical papers and 7 book chapters and has filed more than 25 patents. Andreia is a co-recipient of the ISSCC 2012 Jan Van Vessem Award for Outstanding European Paper and of the ISSCC 2013 Jack Kilby Award for Outstanding Student Paper.
She is as well the winner of the 2012 STMicroelectronics Technology Council Innovation Prize, for having introduced on the company’s roadmap the integrated CMOS THz technology for imaging applications.
Associate Professor, National University of Singapore
Massimo Alioto was born in Brescia in 1972. He took the M.Sc. degree in Electronic Engineering in 1997, and the Ph.D. degree in 2001 from the University of Catania. He is currently Associate Professor at the ECE department of the National University of Singapore, where he leads the Green IC group and is Director of the Integrated Circuits and Embedded Systems area.
In 2002, he joined the Department of Information Engineering of the University of Siena as a Research Associate, where he became Assistant Professor (2002) and Associate Professor (2005). In the summer of 2007, he was visiting professor at EPFL – Lausanne (Switzerland). In 2009-2011, he was visiting professor at the Berkeley Wireless Research Center (BWRC) at the University of California, Berkeley. In 2011-2012, he was visiting professor at the University of Michigan, Ann Arbor. In 2013, he was visiting scientist at Circuit Research Lab – Intel Labs (Hillsboro, OR – USA).
Fellow NXP Semiconductors
Rob Cosaro has been in the semiconductor industry for over 18 years and before that designed power subsystems and data handling subsystems for the space industry. He first started in the semiconductor industry at Philips Semiconductor where he was a design engineer working on 8051 products and later moved on to designing ARM based processors. Philips semiconductor became NXP and while at NXP Rob became Senior Director of Architecture and Systems responsible for all LPC products and was responsible for the first dual core architecture that included a cortex M4 and M0. He is now a Fellow at NXP where is working on low power I.MX application processors, cross over processors and micro-controllers.