2018 Call for Papers

The IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (IEEE S3S)

2018 IEEE S3S Call for Papers
Deadline Extended: June 11, 2018, 11:59pm PST

Papers in the following areas are requested:
Silicon on Insulator (SOI)
3D Integration
Low-Voltage Devices
Low-Power Circuits

SILICON ON INSULATOR (SOI)

• Fully Depleted Silicon on Insulator Technology
• Advanced Materials, Substrate and Processes
• Device Physics, Characterization and Modelling
• Sensors, MEMS, BioMEMS
• Non-Digital Devices and Applications (RF, High-Voltage, Photonics, Analog…)
• Novel SOI Structures, Circuits and Applications
• SOI Design, Circuits and Applications

3D INTEGRATION

• System in Package
• Through Silicon Via (TSV) Technology
• 3D System Integration
• Fabrication Techniques and Bonding Methods
• Design and Test Methodologies
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technologies
• Heterogeneous Structures
• 3D Manufacturing and Logistics
• Reliability of 3D Circuits
• Fault Tolerant 3D Designs

LOW-VOLTAGE DEVICES

• Low-Dimensional (1D,2D) Transistors
• Tunnel FETs
• Negative Capacitance FETs
• Piezoelectric FETs
• Nano-Electromechanical Switches
• Low Voltage Memory Technologies
• Metal-Insulator Transitional Devices
• Spintronic Devices

LOW-POWER CIRCUITS

• Low-Power and Ultra-Low-Power Digital Circuits
• Energy Efficient Designs and Methodologies
• Power Management Techniques
• Asynchronous Circuits
• Energy Harvesting Solutions
• Low Power, Reliable and Resilient Solutions
• Analog/Mixed-Signal Circuits for Wireless Communications
• Innovative ICs
• Near Threshold and Sub-Threshold Designs
• Low Power Applications: IoT, Automotive, Data Mining…

2018 Call for Papers (download) Deadline Extended: June 11, 2018, 11:59pm PST
Preparation of Abstracts
How to submit your abstract