IEEE S3S Conference

SOI Applications Short Course

An Introduction to SOI applications; from low to smart power applications
The number of mobile subscribers worldwide reached 95.5% of the world’s population in 2014 and is expected to reach 9.3B by 2019. Although our behavior as consumers is constantly redefining the requirements for what we know as the Internet-of-Things (IoT) today, IoT will continue to introduce numerous opportunities for the industry. This fast growing trend is driving end markets towards satisfying stringent demands of mobile connected users. In order to support such growth; low cost, low power, more integration, small form factor and fast time to market remain as key enabling requirements. This short course will discuss the role of SOI engineered substrates in addressing the challenges and needs for ultra-low power to high power SOI applications, including:

‒ FDSOI for digital applications providing attractive power/ performance/cost benefits with added functionality addressing ultra- low power cost sensitive IoT applications
‒ High resistivity SOI for RF applications providing high performance integrated solutions addressing the rapid adoption of wireless standards and the escalating demand for data bandwidth
‒ SOI for emerging Si based Photonics applications enabling data centers to meet the demands of cloud computing and big data applications

Considering the role of cars, smart homes and smart cities in the overall IoT ecosystem, and the continued strive for better reliability and better global efficiency; the short course will also cover the role power SOI plays in providing better performance and higher reliability for automotive and other consumer and industrial smart power applications.

An Introduction to SOI applications: from low to smart power applications
Mariam Sadaka, Soitec

CMOS SOI Technology for High Performance Computing
Terry Hook and Paul Chang, IBM

Introduced over 15 years ago in an IBM PowerPC microprocessor, CMOS SOI technology has remained a mainstay in IBM microprocessors. Now in its 8th generation, in a 22nm technology node, SOI is currently leveraged in both IBM’s POWER8 and z13 Mainframe systems. While this recent partially-depleted SOI implementation remains similar in some respects to previous generations, as microprocessor design points have evolved, different aspects and benefits of SOI have been leveraged. In supporting this latest generation of large scale systems designed for cloud computing and big data analytics, the original capacitance benefits from SOI have given way to other advantages ranging from improved device variability to improved device structure and design. Embedded DRAM in particular heavily leverages unique SOI features, enabling the large high-performance caches featured in these microprocessors. This short course will review these current features, as well as highlight directions taken in future SOI technologies.

Designs of Ultra-Low-Power and Ultra-Low-Leakage 65nm-SOTB LSI for IoT Applications
Koichiro Ishibashi, University of Electro-Communications, Tokyo

SOTB(Silicon On Thin Buried oxide) technology is attractive to achieve low-power and low-leakage LSIs with high-speed and reliable operations. LSIs which exhibit such characteristics are most suitable for various IoT applications such as MCU for energy harvesting, wearable computing, healthcare monitoring, environmental monitoring, and bio-medical electronics.

After fundamental characteristics of the 65nm SOTB technology, I introduce low-leakage and low-power LSI designs followed by IPs which make the LSIs low power and highly reliable.

The LSI designs include 1) 13.4pJ/cycle, 0.14uA 32bit CPU at 14MHz and 0.35V, 2) 1.7mW 192MOPS CMA(Cool Mega Array) at 89MHz and 0.4V, 3) 282uW 16bit DSP at 200MHz and 0.55V, 4) 60us search time of SLID(Search-Less Information Detection) LSI at 50MHz. The IPs include 5) 361nA body bias generator at 0.5V, and 6) Radiation-Hard Flip-Flops which achieve SER of 1/15 of Bulk.

Review of RF SOI Technology: a 10 years economic success story now looking toward 5G
Fred Gianesello, STMicroelectronics

During the past 10 years, RF SOI technology has emerged as a technology of choice in order to reduce the cost of 3G RF Front End Module targeting the smartphone and tablet markets. Moving from III-V to Silicon on Sapphire and finally CMOS SOI, this market grew exponentially to represent now almost 1 million 8 inches wafers per year.

Having been a pioneer of RF SOI Technology development back in 2003, STMicroelectronics proposes here to review the developments performed by our industry during the past 10 years in order to make this market happen. We will also share our vision concerning what we believe to be the next steps of RF SOI technology in the context of 5G challenges and how we envision addressing them by delivering innovation and differentiation to the ecosystem.

In this short course we will review first the economical motivation to move to CMOS SOI describing the technical and economic advantages at application level. Then, a detailed review of the technology developments and associated achieved performances for antenna switches will be proposed. Moving to more integration and a SOC approach, we will then illustrate achieved performances for CMOS SOI PA and FEM passive functions (harmonic filter, directional coupler …).Finally, tunable filter/duplexer topic will be discussed in order to provide some insight concerning ongoing R&D developments and the technical challenges that are industry will have to address in the coming years in order to support the growth of the RF SOI market.

Design Considerations for Space Applications
Tony Amort, Boeing Corporation

The challenge of developing state-of-the-art microelectronics for space applications is mitigating the effects of the space radiation environment. Radiation-hardened-by-Design (RHBD) has been demonstrated as an effective approach to leverage advances in commercial integrated circuit fabrication to provide improved performance, power, availability, and reliability for space applications. Recent work with RHBD in the 32nm SOI technology has demonstrated continued success in using design methods to achieve high levels of radiation hardness. New approaches to hardening mixed-signal designs that take advantage of the properties of SOI processes have been developed. Examples of applications, development considerations, and analysis techniques will be covered in this session.

SOI Nanoelectromechanical Systems (NEMS) VLSI for ‘More Than Moore’ Applications
Philip Feng, Case School of Engineering, Case Western Reserve University

Nanoscience today enables exciting emergences of low-dimensional nanostructures and new materials with previously inaccessible properties. We explore these intriguing properties and their multiphysics coupling effects in rationally designed and engineered nanostructures, to innovate new devices for sensing and information processing. Meantime, scaled Si CMOS transistors have been a hallmark and most powerful nanotechnology in massive real-world practice. At the cross-disciplinary interfaces, nano/microelectromechanical systems (NEMS/MEMS) are offering a spectrum of new functionalities in the ‘More Than Moore’ paradigm. In concert with the fascinating advances being made in Si nanoelectronics, and following the scaling of Si transistors, ultrathin SOI technology has also been enabling a number of attractive emerging devices in NEMS/MEMS domains for integrated signal processing, sensing, and ultralow-power logic computing. We will discuss representative case studies including ultrathin SOI nanowire NEMS resonators, resonant sensors (in physical, chemical and biological domains), radio-frequency (RF) resonant-channel transistors, SOI NEMS oscillators with system-in-package (SiP) and system-on-chip (SoC) integration schemes, and VLSI of SOI NEMS arrays and monolithic integration with SOI nanoelectronics. C1hallenges and advances in design and experimental techniques will also be discussed.

Short Course Tutorial on Monolithic 3D Integration

Technological approaches to CMOS integration
Zvi Or-Bach, Monolithic 3D

3DIC with high density face to face processes
Paul Franzon, NCSU

CEA-Leti Monolithic 3D Technology
Olivier Faynot, CEA-Leti

3D VLSI design – CAD and EDA
Yang Du, Samadi Kambiz, Qualcomm

Case studies for Monolithic 3D
Zvi Or-Bach, Monolithic 3D

Monolithic RRAM
Matt Marinella, Sandia Labs